The present invention relates to integrated circuit (IC) testing, and more particularly, to scan testing of integrated circuits and/or devices.
Integrated circuit may be tested at multiple stages of the hardware manufacturing process and, for some products, for hardware maintenance and/or troubleshooting in a customer's environment. A conventional method of testing ICs, referred to as scan testing, relies on registers (e.g., flip-flops or latches) connected, in a switchable manner, in one or more scan chains that provide access to internal nodes of the IC. Test patterns can be shifted in via the scan chain(s), clock signals can then be pulsed to test the selected IC function, and the results can consequently be shifted out and compared with the expected results to detect whether any test fails.
One problem with conventional scan testing is that it may be possible, in some circuits, to shift sensitive data, such security codes, out of the circuit. Security codes stored in semiconductor chips are widely used, for example, in the telecommunications industry for hardware identification and authentication, to enter a secure state or mode, for data encryption, etc. If the circuitry responsible for handling a security code is accessible via a scan chain, then the data could become susceptible to unauthorized access by switching the IC from functional mode to a scan or debug mode, and/or by manipulating the scan-enable signal to shift out the secure information.
A conventional approach to protect secure information in an IC from scan-based attacks is maintain registers that receive such secure information outside of the scan chains, thereby making them inaccessible from the IC's scan ports. However, a drawback of this approach is a concomitant reduction in the scan-test coverage of the IC. Accordingly, it would be advantageous to be able to maintain secure data without reducing the testability of the IC.